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FEATURES Handles All CDMA Baseband Power Management Six LDOs Optimized for Specific CDMA Subsystems Li-Ion and NiMH Battery Charge Function Ambient Temperature: 20 C to +85 C TSSOP 28-Lead Package Optimized for LSI Logic Baseband Chipset APPLICATIONS CDMA Handsets
CDMA Power Management System ADP3510
FUNCTIONAL BLOCK DIAGRAM
VBAT VBAT2
RTC VIO LDO DIGITAL CORE LDO POWER-UP SEQUENCING AND PROTECTION LOGIC ANALOG LDO TCXO LDO MEMORY LDO REF BUFFER
VTRC
PWRONKEY
VIO
ROWX PWRONIN ALARM PDCAP
VCORE
VAN
VTCXO
VMEM
TCXOEN
GENERAL DESCRIPTION
RESCAP
REFOUT RESET
The ADP3510 is a multifunction power system chip optimized for CDMA handset power management. It contains six specialized LDOs, one to power each of the critical CDMA subblocks. Sophisticated controls are available for power-up during battery charging, keypad interface, and RTC alarm. If a Li-Ion battery is being charged, the charge circuit maintains low current charging during the initial charge phase and provides an end of charge (EOC) signal when the cell has been fully charged. The ADP3510 is specified over the temperature range of -20C to +85C and is available in a narrow body TSSOP 28-Lead package.
CHRDET EOC CHGEN GATEIN BATSNS ISENSE GATEDR CHRIN BATTERY CHARGE CONTROLLER
BATTERY VOLTAGE DIVIDER
MVBAT
DGND
ADP3510
AGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
ADP3510-SPECIFICATIONS C (-20
Parameter SHUTDOWN SUPPLY CURRENT VBAT 2.5 V (Deep Discharged Lockout Active) 2.5 V < VBAT 3.2 V (UVLO Active) VBAT >3.2 V OPERATING GROUND CURRENT All LDOs On Except TCXO All LDOs On All LDOs On ICC
ELECTRICAL CHARACTERISTICS1 VTCXO = 0.47
Symbol
TA
+85 C, VBAT = VBAT2 = 3.2 V-7.5 V, CVIO = CVCORE = CVAN = CVMEM = 2.2 F, F, CVBAT = 10 F, min. loads applied on all outputs, unless otherwise noted.)
Min Typ Max Unit
Conditions
VBAT = VBAT2 = 2.3 V VBAT = VBAT2 = 3.15 V VBAT = VBAT2 = 4.0 V IGND Minimum Loads Minimum Loads Maximum Loads
5 30 45 300 340 2.0
15 55 60 390 430 3.5
mA mA mA mA mA % of
Max Load
Current UVLO ON THRESHOLD UVLO HYSTERESIS DEEP DISCHARGED LOCKOUT ON THRESHOLD DEEP DISCHARGED LOCKOUT HYSTERESIS INPUT HIGH VOLTAGE (PWRONIN, TCXOEN, CHGEN, GATEIN) INPUT LOW VOLTAGE (PWRONIN, TCXOEN, CHGEN, GATEIN) INPUT HIGH BIAS CURRENT (PWRONIN, TCXOEN, CHGEN, GATEIN) INPUT LOW BIAS CURRENT (PWRONIN, TCXOEN, CHGEN, GATEIN) PWRONKEY INPUT HIGH VOLTAGE PWRONKEY INPUT LOW VOLTAGE PWRONKEY INPUT PULLUP RESISTANCE TO VBAT THERMAL SHUTDOWN THRESHOLD ROWX CHARACTERISTICS ROWX Output Low Voltage ROWX Output High Leakage Current I/O LDO (VIO) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage DIGITAL CORE LDO (VCORE) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability
2
VBAT VBAT VBAT VBAT VIH VIL IIH
3.1 2.0
3.2 200 2.4 100
3.3 2.75
V mV V mV V
2.0 0.4 1.0
V mA mA
IIL
-1.0
VIH VIL
0.7
VBAT 0.3
V VBAT V 145 kW C C 0.4 1 V mA
70
105 150 25
THERMAL SHUTDOWN HYSTERESIS VOL IL PWRONKEY = Low IOL = 200 mA PWRONKEY = High V(ROWX) = 5 V Line, Load, Temp Minimum Load 50 mA ILOAD 25 mA VO = VINITIAL - 100 mV ILOAD = 25 mA Line, Load, Temp Minimum Load 50 mA ILOAD 120 mA 1.78 2.85
VIO DVIO DVIO CO VDO
2.935 1 3
3.02
2.2 50 1.85 1 8 150 1.92
V mV mV mF mV V mV mV mF
VCORE DVCORE DVCORE CO
2.2
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ADP3510
Parameter ANALOG LDO (VAN) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage Symbol VAN DVAN DVAN CO VDO DVBAT/ DVAN VNOISE Conditions Line, Load, Temp Minimum Load 50 mA ILOAD 75 mA VO = VINITIAL 100 mV ILOAD = 75 mA f = 217 Hz (T = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 75 mA VBAT = 3.6 V Line, Load, Temp Minimum Load 50 mA ILOAD 10 mA VO = VINITIAL - 100 mV ILOAD = 10 mA f = 217 Hz (T = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 10 mA VBAT = 3.6 V 2.71 Min 2.85 Typ Max Unit V mV mV mF mV dB mV rms 2.935 3.02 1 6
2.2 100 75 80 175
TCXO LDO (VTCXO) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage
VTCXO DVTCXO DVTCXO CO VDO DVBAT/ DVTCXO VNOISE
2.765 2.82 1 3 175 75 80
0.47
V mV mV mF mV dB mV rms
REAL-TIME CLOCK LDO/ BATTERY CHARGER (VRTC) Maximum Output Voltage Off Reverse Input Current Dropout Voltage MEMORY LDO (VMEM) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage REFOUT Output Voltage Line Regulation Load Regulation Ripple Rejection Maximum Capacitive Load Output Noise Voltage RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Output Current Delay Time per Unit Capacitance Applied to RESCAP Pin SEQUENCING Delay Time per Unit Capacitance Applied to PDCAP Pin PDCAP Charging Current VAN Discharge Resistance VIO Discharge Resistance REV. 0
VRTC IL VDO
1 mA ILOAD 6 mA 2.0 V < VBAT < UVLO VO = VINITIAL - 100 mV ILOAD = 10 mA Line, Load, Temp Minimum Load 50 mA ILOAD 60 mA VO = VINITIAL - 100 mV ILOAD = 60 mA
2.77
2.85
2.93 1 175
V mA mV
VMEM DVMEM DVMEM CO VDO
2.85
2.935 3.02 1 5 2.2 100 175
V mV mV mF mV
VREFOUT Line, Load, Temp DVREFOUT Minimum Load DVREFOUT 0 mA ILOAD 50 mA VBAT = 3.6 V DVBAT/ f = 217 Hz (T = 4.6 ms) DVREFOUT VBAT = 3.6 V CO VNOISE f = 10 Hz to 100 kHz VOH VOL IOL/IOH TD IOH = +500 mA IOL = -500 mA
1.19
1.210 1.23 0.3 0.6 75 100 40
V mV mV dB pF mV rms V V mA ms/nF
2.4 0.25 1 4.0
0.8
1.5
TD IOH VPDCAP = 0
0.3 2.5
0.8 5 200 200
3.0 8
ms/nF mA W W
-3-
ADP3510
Parameter BATTERY VOLTAGE DIVIDER Divider Ratio Divider Impedance at MVBAT Divider Leakage Current Divider Resistance BATTERY CHARGER Charger Output Voltage Symbol Conditions Min 2.94 50 230 Typ 3.00 80 350 Max 3.06 110 1 430 Unit BATSNS/MVBAT TCXOEN = High ZO TCXOEN = Low TCXOEN = High BATSNS
kW mA kW V
Charger Output Voltage Load Regulation
BATSNS BATSNS
CHRDET on Threshold CHRDET Hysteresis CHRDET Off Delay3 CHRIN Supply Current Current Limit Threshold High Current Limit (100%: UVLO Not Active) Low Current Limit (10%: UVLO Active) ISENSE Bias Current End of Charge Signal Threshold
CHRIN-VBAT
4.5 V < CHRIN < 10 V, 4.158 4.200 4.242 CHGEN = Low, TA = 0C to 50C CHRIN = 10 V, VSENSE = 10 mV, 4.162 4.200 4.238 TA = 0C to 50C CHRIN = 5 V, 2 8 0 < CHRIN - ISENSE < Current Limit Threshold, CHGEN = Low VBAT = 3.6 V 260 70 CHRIN < VBAT 6 CHRIN = 5 V 0.6 1 CHRIN = 5 V dc VBAT = 3.6 V CHGEN = Low CHRIN = 5 V VBAT = 2 V CHGEN = Low CHRIN = 5 V 150 172 195
V mV
mV mV ms/nF mA mV
CHRIN-ISENSE
2
15
30
mV mA mV
180 2 12
250 26
CHRIN-ISENSE
End of Charge Reset Threshold GATEDR Transition Time
VBAT t R , tF
CHRIN = 5 V dc VBAT > 4.0 V CHGEN = Low CHGEN = Low CHRIN = 5 V VBAT > 3.6 V CHGEN = High, CL = 2 nF CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = High IOH = -1 mA CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = Low IOL = +1 mA IOH = -250 mA IOL = +250 mA CHRIN = 7.5 V CHGEN = High GATEIN = Low CHRIN = 7.5 V CHGEN = High GATEIN = Low
3.82 1
3.96
4.10 10
V ms
GATEDR High Voltage
VOH
4.5
V
GATEDR Low Voltage
VOL
0.5
V
Output High Voltage (EOC, CHRDET) Output Low Voltage (EOC, CHRDET) Battery Overvoltage Protection Threshold (GATEDRAEHigh) Battery Overvoltage Protection Hysteresis
VOH VOL BATSNS
2.4 0.25 5.30 5.50 5.70
V V V
BATSNS
400
mV
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125 C. Operation beyond 125 C could cause permanent damage to the device. 3 Delay set by external capacitor on the RESCAP pin. Specifications subject to change without notice.
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ADP3510
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Voltage on any pin with respect to any GND Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +10 V Voltage on any pin may not exceed VBAT, with the following exceptions: CHRIN, GATEDR, ISENSE Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Ambient Temperature Range . . . . -20C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C qJA, Thermal Impedance (TSSOP-28) 2-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98C/W 4-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68C/W Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
Model ADP3510ARU
Temperature Range -20C to 85C
Package Option RU-28
PIN CONFIGURATION
PWRONIN PWRONKEY ROWX ALARM PDCAP VRTC BATSNS MVBAT CHRDET
1 2 3 4 5 6 7 8 9 28 27 26 25 24
PIN FUNCTION DESCRIPTIONS
Pin
TCXOEN AGND REFOUT VTCXO VAN VBAT VCORE VMEM VBAT2 VIO RESET RESCAP CHGEN EOC
Mnemonic PWRONIN
Function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
ADP3510
TOP VIEW (Not to Scale)
23 22 21 20 19 18 17 16 15
CHRIN 10 GATEIN 11 GATEDR 12 DGND 13 ISENSE 14
Power-On/-Off Signal from Microprocessor PWRONKEY Power-On/-Off Key ROWX Power Key Interface Output ALARM Alternative Power-On PDCAP Power-On Delay Timer Capacitor VRTC VRTC LDO Output BATSNS Battery Voltage Sense Input MVBAT Divided Battery Voltage Output CHRDET Charge Detect Output CHRIN Charger Input Voltage GATEIN Microprocessor Gate Input Signal GATEDR Gate Drive Output DGND Digital Ground ISENSE Charge Current Sense Input EOC End of Charge Signal CHGEN Charger Enable for GATEIN, NiMH Pulse Charging RESCAP Reset Delay Time RESET Main Reset VIO I/O LDO Output VBAT2 Battery Input Voltage 2 VMEM Memory LDO Output VCORE Digital Core LDO Output VBAT Battery Input Voltage VAN Analog LDO Output VTCXO TCXO LDO Output REFOUT Output Reference AGND Analog Ground TCXOEN TCXO LDO Enable and MVBAT Enable
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3510 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADP3510
Table I. LDO Control Logic
AR EY ET NK NI N or AL M
EN
RE
LO *
RD
RO
RO
EM
LO
AT M VB
O
XO
VR TC
VA N
PW
VI O
CH
PW
D
CX
O
VC
Phone Status State #1 battery deep discharged State #2 phone off State #3 phone off, turn on allowed State #4 charger applied State #5 phone turned on by user key State #6 phone turned on by BB State #7 phone and TCXO LDO kept on by BB L H H H H H X L H H H H X X L H X L X X H X L H X X L X X H X X X L L L OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON OFF OFF OFF ON ON OFF OFF OFF OFF ON ON ON OFF ON ON ON ON ON OFF OFF OFF OFF OFF OFF
VT
VM
UV
TC
D
OFF** ON OFF** ON OFF ON
H
H
L
H
H
H
ON
ON
ON
ON
ON
ON
ON
*UVLO is only active when phone is turned off. UVLO is ignored once the phone is turned on. **Controlled by TCXOEN.
-6-
RE
ON
REV. 0
FO
UT
ADP3510
VBAT 23 VBAT2 20 IO LDO VBAT VREF DEEP DISCHARGED UVLO UVLO EN DGND OUT PG 19 VIO
ADP3510
110k PWRONKEY ROWX 2 3
UVLO
S Q R
DIGITAL CORE LDO OVER TEMP SHUTDOWN VBAT VREF OUT 22 VCORE
PWRONIN ALARM
1 4
EN
DGND
ANALOG LDO VBAT CHARGER DETECT VREF EN AGND OUT 24 VAN
TCXOEN 28 RESCAP 17 CHRDET 9 RESET GENERATOR TCXO LDO VBAT VREF EOC 15 CHGEN 16 GATEIN 11 BATSNS ISENSE 7 14 RTC LDO DGND VBAT VREF EN DGND OUT 6 VRTC LI-ION BATTERY CHARGE CONTROLLER AND PROCESSOR CHARGE INTERFACE EN AGND OUT 25 VTCXO 18 RESET
MEMORY LDO VBAT VREF EN DGND OUT PG 21 VMEM
GATEDR 12 CHRIN 10
POWERON DELAY MVBAT
EN REF BUFFER
26 REFOUT
8
1.21V
27 AGND 13 DGND
AGND 5 PDCAP
Figure 1. Functional Block Diagram
EOC CHGEN GATEIN CHRIN (10V MAX) ISENSE GATEDR BATSNS CHRDET
ADP3510
BATTERY CHARGE CONTROLLER
Figure 2. Battery Charger Typical Application
REV. 0
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ADP3510 --Typical Performance Characteristics (VBAT = 3.6 V, T = 25 C, unless otherwise specified.)
A
400
400
160 140 +85 C +25 C
350
A
ALL LDO, MVBAT, REFOUT ON, MIN LOAD (TCXOEN = H)
350
ALL LDO, MVBAT, REFOUT, ON MIN LOAD (TCXOEN = H)
I VRTC - A
120 100 80
IGND - A
IGND -
300 VIO, VCORE, VMEM, VRTC, VAN, REFOUT ON, MIN LOAD (TCXOEN = L) 250
300 VIO, VCORE, VMEM, VRTC, VAN, REFOUT, ON MIN LOAD (TCXOEN = L) 250
-20 C 60 40 20
200 3.0
200
3.5 4.0 4.5 VBAT - V 5.0 5.5
40
20
0
20
40
60
80
100 120
TEMPERATURE - C
10 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 VRTC - V
TPC 1. Ground Current vs. Battery Voltage
180 160
TPC 2. Ground Current vs. Temperature
TPC 3. RTC I/V Characteristic
1.8
A
1.6
DROPOUT VOLTAGE - mV
REVERSE LEAKAGE CURRENT -
VTCXO 140 120
3.5V VBAT 3.3V
1.4 1.2 1.0 0.8 0.6 0.4 0.2
RTC REVERSE LEAKAGE (VBAT = FLOAT)
100 80 60 40 20 0 0 20 40 60 LOAD CURRENT - mA 80 VSIM VMEM
VTCXO VMEM
RTC REVERSE LEAKAGE (VBAT = 2.3V)
10mV/DIV 10mV/DIV
0 25 30 35 40 45 50 55 60 65 70 75 80 85 TEMPERATURE - C
TIME
100 s/DIV
TPC 4. VTRC Reverse Leakage Current vs. Temperature
TPC 5. Dropout Voltage vs. Load Current
TPC 6. Line Transient Response, Minimum Loads
3.5V
3.5V
3.5V
3.3V
VBAT
3.3V
VBAT VAN 10mV/DIV 10mV/DIV 2mV/DIV
3.3V
VBAT VAN VCORE VIO 10mV/DIV 10mV/DIV 2mV/DIV
VTCXO VMEM
10mV/DIV 10mV/DIV
VCORE VIO
TIME
100 s/DIV
TIME
100 s/DIV
TIME
100 s/DIV
TPC 7. Line Transient Response, Maximum Loads
TPC 8. Line Transient Response, Minimum Loads
TPC 9. Line Transient Response, Maximum Loads
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ADP3510
10mA LOAD 1mA
LOAD 25mA
60mA
2mA
LOAD
VTCXO 10mV/DIV
VIO 5mV/DIV
5mA
VMEM
10mV/DIV
TIME
200 s/DIV
TIME
200 s/DIV
TIME
200 s/DIV
TPC 10. VTCXO Load Step
TPC 11. VIO Load Step
TPC 12. VMEM Load Step
120mA 75mA PWRONIN (2V/DIV) LOAD VCORE 10mV/DIV VAN 10mV/DIV VCORE (200mV/DIV) TIME 200 s/DIV TIME - 200 s/DIV TIME 200 s/DIV 10mA LOAD 8mA PDCAP = 1nF VIO (200mV/DIV) VAN (200mV/DIV)
TPC 13. VCORE Load Step
TPC 14. VAN Load Step
TPC 15. Turn On Transient by PWRONIN, Minimum Load
PWRONIN (2V/DIV) REFOUT (200mV/DIV)
PWRONIN (2V/DIV)
PWRONIN (2V/DIV) REFOUT (200mV/DIV) PDCAP = 1nF
PDCAP = 1nF VMEM (200mV/DIV) VTCXO (200mV/DIV) PDCAP = 1nF
VAN (200mV/DIV) VIO (200mV/DIV)
VMEM (200mV/DIV) VTCXO (200mV/DIV)
VCORE (200mV/DIV)
TIME
200 s/DIV
TIME
200 s/DIV
TIME
200 s/DIV
TPC 16. Turn On Transient by PWRONIN, Minimum Load
TPC 17. Turn On Transient by PWRONIN, Maximum Load
TPC 18. Turn On Transient by PWRONIN, Maximum Load
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ADP3510
4.25 4.24 4.23 4.22 4.21 4.20 4.19 4.18 4.17 4.16 4.15 -40 -20 VIN = 5.0V ILOAD = 10mA
4.22 VIN = 5V RSENSE = 250m
OUTPUT VOLTAGE - V
OUTPUT VOLTAGE - V
4.210 RSENSE = 250m ILOAD = 500mA 4.205
4.21
CHARGER VOUT - V
4.20
4.200
ILOAD = 10mA 4.195
4.19
4.18
0 20 40 60 80 TEMPERATURE - C 100 120
4.190
0 200 400 600 ILOAD - mA 800 1000
5
6
7 8 INPUT VOLTAGE - V
9
10
TPC 19. Charger VOUT vs. Temperature, VIN = 5.0 V, ILOAD = 10mA
TPC 20. Charger VOUT vs. ILOAD (VIN = 5.0 V)
TPC 21. Charger VOUT vs. VIN
THEORY OF OPERATION
The ADP3510 is a total solution power management chip for use with CDMA baseband chipsets and is optimized for the CBP3.0/ 4.0 type chipsets. Figure 1 shows a block diagram of the ADP3510. The ADP3510 contains several blocks: Six Low Dropout Regulators (Input-Output, Core, Analog, Crystal Oscillator, Memory, Realtime Clock) Reset Generator Buffered Precision Reference Lithium Ion Charge Controller and Processor Interface Power-On/-Off Logic Undervoltage Lockout Deep Discharge Lockout
These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. The ADP3510 combines the benefits of both worlds by providing an integrated standard product where every block is optimized to operate in a CDMA environment while maintaining a cost-competitive solution. Figure 3 shows the external circuitry associated with the ADP3510. Only a minimal number of support components are required.
Input Voltage
The input voltage range of the ADP3510 is 3.2 V to 7.5 V and is optimized for a single Li-Ion cell or three NiMH cells. The thermal impedance of the ADP3510 is 68C/W for four layer boards. The end of charge voltage for high capacity NiMH cells can be as high as 5.5 V. Power dissipation should be calculated at maximum ambient temperatures and battery voltage in order not to exceed the 125C maximum allowable junction temperature. Figure 4 shows the maximum power dissipation as a function of ambient temperature.
ADP3510
PWRON PWRONKEY KEYPADROW ALARM VRTC
1 2 3 4 5
PWRONIN PWRONKEY ROWX ALARM PDCAP VRTC BATSNS MVBAT CHRDET CHRIN GATEIN GATEDR DGND ISENSE
TCXOEN 28 AGND 27 REFOUT 26 VTCXO 25 VAN 24 VBAT 23 VCORE 22 VMEM 21 VBAT2 20 VIO 19 RESET 18 RESCAP 17 CHGEN 16 EOC 15 C5 0.1 F C6 2.2 F C8 2.2 F C4 10 F C9 2.2 F C10 0.22 F C11 0.1 F R2 10
TCXOEN
REF VTCXO VAN
C1 0.1 F
C2 10nF
6 7 8 9 10
VCORE C7 2.2 F VMEM
ADC GPIO CHARGER IN GPIO R1 0.25 C3 1.0nF
VIO RESET
11 12 13 14
GPIO GPIO
Q1 SI3441DY D1 10BQ015 Li BATTERY
Figure 3. Typical Application Circuit
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ADP3510
1.2 1.0
POWER DISSIPATION - W
(ML614, ML621, or ML1220) from Sanyo. The ML621 has a small physical size (6.8 mm diameter) and will give many hours of backup time. The ADP3510 supplies current both for charging the coin cell and for the RTC module. The nominal charging voltage is 2.85 V, which ensures long cell life while obtaining in excess of 90% of the nominal capacity. In addition, it features a very low quiescent current since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage, which is needed when the main battery is removed and the coin cell supplies the RTC module.
IO LDO (VIO)
0.8
0.6
0.4
0.2
0.0 -20
0
20 40 60 AMBIENT TEMPERATURE - C
80
100
Figure 4. Power Dissipation vs. Temperature
The IO LDO generates the voltage needed for the peripheral subsystems of the baseband processor, including GPIO, display, and serial interfaces. It is rated for 25 mA of supply current and is controlled by the power-on delay block of the ADP3510.
Reference Output (REFOUT)
However, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. In this mode, there is a relatively light load on the LDOs. A fully charged Li-Ion battery is 4.245 V, where the ADP3510 can deliver the maximum power (0.52 W) up to 85C ambient temperature.
Low Dropout Regulators (LDOs)
The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.65% over temperature. The reference can be used with the baseband converter, if the converter's own reference is not accurate. This may significantly reduce the calibration time needed for the baseband converter during production.
Power ON/OFF
The ADP3510 high performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, regulation, ripple rejection, and output noise. 2.2 mF tantalum or MLCC ceramic capacitors are recommended for use with the core, memory, IO, and analog LDOs. A 0.22 mF capacitor is recommended for the TCXO LDO.
Digital Core LDO (VCORE)
The ADP3510 handles all issues regarding the powering ON and OFF of the handset. It is possible to turn on the ADP3510 in four different ways: Pulling the PWRONKEY Low Pulling PWRONIN High Pulling ALARM High CHRIN Exceeds CHRDET Threshold Pulling the PWRONKEY low is the normal way of turning on the handset. This will turn on all the LDOs, as long as the PWRONKEY is held low. When the VIO LDO comes into regulation, the RESET timer is started. After timing out, the RESET pin goes high, allowing the baseband processor to start up. With the baseband processor running, it can poll the ROWX pin of the ADP3510 to determine if the PWRONKEY has been depressed and pull PWRONIN high. Once the PWRONIN is taken high, the PWRONKEY can be released. Note that by monitoring the ROWX pin, the baseband processor can detect a second PWRONKEY press and turn the LDOs off in an orderly manner. In this way, the PWRONKEY can be used for ON/OFF control. Pulling the ALARM pin high is how the alarm in the realtime clock module will turn the handset on. Asserting ALARM will turn the core, IO, memory, and analog LDOs on, starting up the baseband processor. Applying an external charger can also turn the handset on. This will turn on all the LDOs, again starting up the baseband processor. Note that if the battery voltage is below the undervoltage lockout threshold, applying the adapter will not start up the LDOs.
The digital core LDO supplies the baseband circuitry in the handset (baseband processor and baseband converter). The LDO has been optimized for very low quiescent current at light loads as this LDO is on at all times.
Memory LDO (VMEM)
The memory LDO supplies the memory of the baseband processor. The memory LDO is capable of supplying 60 mA of current and has also been optimized for low quiescent current and will power up at the same time as the core LDO.
Analog LDO (VAN)
This LDO has the same features as the core LDO. It has furthermore been optimized for good low frequency ripple rejection for use with the baseband converter sections in order to reject the ripple coming from the RF power amplifier. VAN is rated to 75 mA load, which is sufficient to supply the complete analog section of the baseband converter. The analog LDO is controlled by the power-on delay block of the ADP3510.
TCXO LDO (VTCXO)
The TCXO LDO is intended as a supply for a temperature compensated crystal oscillator, which needs its own ultralow noise supply. VTCXO is rated for 10 mA of output current and is turned on when TCXOEN is asserted.
RTC LDO (VRTC)
The RTC LDO charges up a rechargeable lithium type coin cell to run the realtime clock module. It has been designed to charge manganese lithium batteries such as the ML series
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ADP3510
Power On Delay
The power-on delay block in the ADP3510 controls the turn-on sequence of VCORE, VIO, and VAN. Asserting a power-on in one of the four above methods will start the LDOs in the following sequence: 1. The VMEM LDO will start up. 2. The VIO and VAN outputs will be discharged by the poweron delay block. The discharge delay time is set by the value of the PDCAP. 3. After the discharge time has expired, the VCORE LDO is allowed to start up. 4. When the output of VCORE exceeds 1.2 V, the VIO and VAN LDOs are allowed to start up. The power-on delay is set by an external capacitor on PDCAP: ms CPDCAP nF See Figure 5 for the power-up timing sequence. t PD = 0.8
INTERNAL POWER ON* 1.8V VCORE 1.2V
Once the system is started and the core, memory, analog, and IO LDOs are up and running, the UVLO function is entirely disabled. The ADP3510 is then allowed to run until the battery voltage reaches the DDLO threshold, typically 2.4 V. Normally, the battery voltage is monitored by the baseband processor and usually shuts the phone off at around 3.0 V. If the handset is off and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and puts the ADP3510 into UVLO shutdown mode. In this mode, the ADP3510 draws very low quiescent current, typically 30 mA. The RTC LDO is still running until the DDLO disables it. In this mode, the ADP3510 draws 5 mA of quiescent current. NiMH batteries can reverse polarity if the 3-cell battery voltage drops below 3.0 V, which will degrade the battery's performance. Lithium Ion batteries will lose their capacity if over discharged repeatedly so minimizing the quiescent currents helps prevent battery damage.
RESET
(1)
The ADP3510 contains a reset circuit that is active both at power-up and power-down. The RESET pin is held low at initial powerup. An internal power good signal is generated by the IO LDO when its output is in regulation which starts the reset delay timer. The delay is set by an external capacitor on RESCAP:
3.0V VMEM
ms CRESCAP (2) nF Should the IO or MEM LDO drop out of regulation, the RESET signal will go low and remain low until the IO and MEM LDO outputs are back in regulation and the RESET timer has timed out. At power-off, RESET will be kept low to prevent any baseband processor starts. t RESET = 1.5
Over-Temperature Protection
3.0V V10, VAN
*PWRONIN or CHRDET or ALARM or PWRONKEY
POWER-ON DELAY
V10, VAN < VCORE UNTIL VCORE > 1.2V
Figure 5. Power-Up Timing Diagram
Deep Discharge Lockout (DDLO)
In case of a failure that causes excess power dissipation to the IC, the thermal shutdown function will be activated. The maximum die temperature for the ADP3510 is 125 C. If the die temperature exceeds 160 C, the ADP3510 will disable all the LDOs except the RTC LDO. The LDOs will not be re-enabled before the die temperature is below 125 C, regardless of the state of PWRONKEY, PWRONIN, ALARM, and CHRDET. This ensures that the handset will always power-off before the ADP3510 exceeds its absolute maximum thermal ratings.
Battery Charging
The DDLO block in the ADP3510 will shut down the handset in the event the software fails to turn off the phone when the battery drops below 2.9 V to 3.0 V. The DDLO will shut down the handset when the battery falls below 2.4 V to prevent further discharge and damage to the cell.
Undervoltage Lockout (UVLO)
The ADP3510 battery charger can be used with lithium ion (Li+) and nickel metal hydride (NiMH) batteries. The charger initialization, trickle charging, and Li+ charging are implemented in hardware. Battery type determination and NiMH charging must be implemented in software. The charger block works in three different modes: Low Current (Trickle) Charging Lithium Ion Charging Nickel Metal Hydride Charging See Figure 6 for the battery charger flowchart.
The UVLO function in the ADP3510 prevents startup when the initial voltage of the battery is below the 3.2 V threshold. If the battery voltage is this low with no load, there is insufficient capacity left to run the handset. When the battery is greater than 3.2 V, such as inserting a fresh battery, the UVLO comparator trips and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery decays to below 3.0 V. Note that the DDLO has enabled the RTC LDO under this condition.
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ADP3510
NONCHARGING MODE
poll the battery to determine which chemistry is present and set the charger to the proper mode.
Lithium Ion Charging
CHARGER DETECTED CHRIN > BATSNS YES
NO
For lithium ion charging, the CHGEN input must be low. This allows the ADP3510 to continue charging the battery at the full current. The full charge current can be calculated by using:
ICHR ( FULL ) =
VBAT > UVLO YES
172 mV RSENSE
(4)
NO LOW CURRENT CHARGE MODE VSENSE = 15mV BATTERY TYPE NiMH
Li CHGEN = LOW
CHGEN = HIGH
NiMH CHARGING MODE GATEIN = PULSED
HIGH CURRENT CHARGE MODE VSENSE = 172mV NO VBAT > 5.5V
If the voltage at BATSNS is below the charger's output voltage of 4.2 V, the battery will continue to charge in the constant current mode. If the battery has reached the final charge voltage, a constant voltage is applied to the battery until the charge current has reduced to the charge termination threshold. The charge termination threshold is determined by the voltage across the sense resistor. If the battery voltage is above 4.0 V and the voltage across the sense resistor has dropped to 12 mV, then an end of charge signal is generated and the EOC output goes high (see Figure 7). The baseband processor can either let the charger continue to charge the battery for an additional amount of time or terminate the charging. To terminate the charging, the processor must pull the GATEIN and CHGEN pins high.
4.2V
NO VBAT > 4.2V YES NiMH CHARGER OFF GATEIN = HIGH
YES
VBAT 3.2V
CONSTANT VOLTAGE MODE VBAT < 5.5V NO HIGH CURRENT NO END OF CHARGE VSENSE < 12mV YES EOC = HIGH YES ICHARGE 0 LOW CURRENT EOC CURRENT
TERMINATE CHARGE CHREN = HIGH GATEIN = HIGH EOC INDICATOR
Figure 6. Battery Charger Flowchart
Trickle Charging
Figure 7. Lithium Ion Charging Diagram
NiMH Charging
When the battery voltage is below the UVLO threshold, the charge current is set to the low current limit, or about 10% of the full charge current. The low current limit is determined by the voltage developed across the current sense resistor. Therefore, the trickle charge current can be calculated by:
ICHR (TRICKLE ) =
15 mV RSENSE
(3)
For NiMH charging, the processor must pull the CHGEN pin high. This disables the internal Li+ mode control of the gate drive pin. The gate drive must now be controlled by the baseband processor. By pulling GATEIN high, the GATEDR pin is driven high, turning the PMOS off. By pulling the GATEIN pin low, the GATEDR pin is driven low, and the PMOS is turned on. So, by pulsing the GATEIN input, the processor can charge a NiMH battery. Note that when charging NiMH cells, a current limited adapter is required. During the PMOS off periods, the battery voltage needs to be monitored through the MVBAT pin. The battery voltage is continually polled until the final battery voltage is reached. Then the charge can either be terminated or the frequency of the pulsing reduced. An alternative method of determining the end of charge is to monitor the temperature of the cells and terminate the charging when a rapid rise in temperature is detected.
Trickle charging is performed for deeply discharged batteries to prevent undue stress on either the battery or the charger. Trickle charging will continue until the battery voltage exceeds the UVLO threshold. Once the UVLO threshold has been exceeded, the charger will switch to the high current limit, the LDOs will start up, and the baseband processor will start to run. The processor must then REV. 0
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ADP3510
Battery Voltage Monitoring Power-On Delay Capacitor Selection
The battery voltage can be monitored at MVBAT during charging and discharging to determine the condition of the battery. An internal resistor divider is connected to BATSNS when both the baseband processor and the crystal oscillator are powered up. To enable MVBAT, both PWRONIN and TCXOEN must be high. The ratio BATSNS/MVBAT of the voltage divider is set to 3.0. The divider will be disconnected from the battery when the baseband processor is powered down.
Charge Detection
The PDCAP sets the interval that the VAN and VIO LDOs are discharged. To ensure that the baseband processor is properly reset, the VIO and VAN LDOs should be fully discharged before power is reapplied. The discharge time can be estimated using:
t PD = 900 COUT SEC
(6)
where tPD is the discharge time, and COUT is the VIO or VAN LDO output capacitor value. The power-on delay is set by an external capacitor on PDCAP. For worst-case delay: t PD = 0.3 CPDCAP ms CPDCAP or nF nF = t PD 3.33 ms
The ADP3510 charger block has a detection circuit that determines if an adapter has been applied to the CHRIN pin. If the adapter voltage exceeds the battery voltage by 260 mV, the CHRDET output will go high. If the adapter is then removed or the voltage at the CHRIN pin drops to around 190 mV above the BATSNS pin, then CHRDET goes low.
APPLICATION INFORMATION Input Capacitor Selection
(7)
So, for a 2.2 mF output capacitor, the required delay is about 2 ms. This results in a 6.8 nF PDCAP value.
Setting the Charge Current
For the input (VBAT and VBAT2) of the ADP3510, a local bypass capacitor is recommended. Use a 10 mF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 mF tantalum capacitor with a small (1 mF to 2 mF) ceramic in parallel. A separate input for the IO LDO is supplied for additional bypassing or filtering. The IO LDO has VBAT2 as its input.
LDO Capacitor Selection
The ADP3510 is capable of charging both lithium ion and NiMH batteries. For NiMH batteries, the charge current is limited by the adapter. For lithium ion batteries, the charge current is programmed by selecting the sense resistor, R1. The lithium ion charge current is calculated using:
ICHR =
VSENSE 172 mV = R1 R1
(8)
The performance of any LDO is a function of the output capacitor. The core, memory, IO, and analog LDOs require a 2.2 mF capacitor, and the TCXO LDO requires a 0.22 mF capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR (any CAP technology). The ADP3510 is stable with extremely low ESR capacitors (ESR ~ 0), such as multilayer ceramic capacitors, but care should be taken in their selection. Note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. A good quality dielectric capacitor, X7R or better, is recommended. The RTC LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 mF ceramic capacitor is recommended for stability and best performance.
RESET Capacitor Selection
Where VSENSE is the high current limit threshold voltage. Or, if the charge current is known, R1 can be found:
R1 =
VSENSE 172 mV = ICHR ICHR
(9)
Similarly the trickle charge current and the end of charge current can be calculated: ITRICKLE = VSENSE 15 mV = R1 R1
I EOC =
VSENSE 12 mV = R1 R1
(10)
RESET is held low at power-up. An internal power-good signal starts the reset delay when the IO LDO is up. The delay is set by an external capacitor on RESCAP:
Example: Assume a 850 mA-H capacity lithium ion battery and a 1 C charge rate. R1 = 200 m . Then ITRICKLE = 75 mA and IEOC = 60 mA. Appropriate sense resistors are available from the following vendors: Vishay Dale IRC Panasonic
Charger FET Selection
tRESET = 1.5 ms / nF CRESCAP
(5)
A 100 nF capacitor will produce a 150 ms reset delay. The current capability of RESET is minimal (a few hundred nA) when VIO is off to minimize power consumption. When VIO is on, RESET is capable of driving 500 mA.
The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and the charge current. The selected PMOS must satisfy the physical, electrical, and thermal design requirements.
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ADP3510
To ensure proper operation, the minimum VGS the ADP3510 can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following:
VGS = VADAPTER( MIN ) - VSENSE - VGATEDR
VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT
= 5 V - 0.5 V - 0.170 V - 4.2 V = 130 mV RDS (ON ) = = 153 mW VDS 130 mV = I CHR( MAX ) 850 mV
(15)
(11)
where: VADAPTER(MIN) is the minimum adapter voltage. VDIODE is the maximum forward drop of the charger diode, D1. VGATEDR is the gate drive "low" voltage, 0.5 V. VSENSE is the maximum high current limit threshold voltage. The difference between the adapter voltage (VADAPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the ON resistance of the FET at maximum charge current.
VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT
(16)
PDISS = VADAPTER( MAX ) - VDIODE - VSENSE - UVLO I CHR
PDISS = (6.5 V - 0.5 V - 0.170 V - 3.2) 0 / 85 A = 2.24 W Appropriate PMOS FETs are available from the following vendors: Siliconix IR Fairchild
Charger Diode Selection
(
)
(12)
Then the RDS(ON) of the FET can be calculated. RDS (ON ) = VDS I CHR( MAX ) (13)
The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using:
PDISS = VADAPTER( MAX ) - VDIODE - VSENSE - UVLO I CHR
It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case, the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an over-specified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design. For example: VADAPTER(MIN) = 5.0 V VADAPTER(MAX) = 6.5 V VDIODE = 0.5 V at 850 mA VGATEDR = 0.5 V VSENSE = 170 mV VGS = 5 V - 0.5 V - 0.170 V = 4.3 V. So choose a low-threshold voltage FET. (14)
(
)
The diode, D1, shown in Figure 3, is used to prevent the battery from discharging through the PMOS' body diode into the charger's internal bias circuits. A Schottky diode is recommended to minimize the voltage difference from the charger to the battery and the power dissipation. Choose a diode with a current rating high enough to handle the battery charging current, a voltage rating greater than VBAT, and a low leakage current. The blocking diode is required for both lithium and nickel battery types.
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed circuit boards: 1. Connect the battery to the VBAT and VBAT2 pins of the ADP3510. Locate the input capacitor as close to the pins as possible. 2. VAN and VTCXO capacitors should be returned to AGND. 3. VCORE, VMEM, and VIO capacitors should be returned to DGND. 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. 5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement. 6. Kelvin connect the charger's sense resistor by running separate traces to the CHRIN pin and ISENSE pin. Make sure that the traces are terminated as close to the resistor's body as possible. 7. Use the best industry practice for thermal considerations during the layout of the ADP3510 and charger components. Careful use of copper area, weight, and multilayer construction all contribute to improved thermal performance.
REV. 0
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ADP3510
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Thin Shrink Small Outline (TSSOP) (RU-28)
C02714-0-5/02(0)
0.028 (0.70) 0.020 (0.50) 0.386 (9.80) 0.378 (9.60)
28
15
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 14
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
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PRINTED IN U.S.A.

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